Standard different threshold devices (eg- Standard Vt and Hight

Standard Cell LibraryStandard cells are designed based on area, performance andpower. The architecture will be decide by cell height which is based on pitch.The track, ? ratio, pitch, and possible PMOS and NMOS width constant forparticular library.Pitch is the distance between two tracks.               Pitch= Metalwidth + Via overhead + Metal-to-metal spacingStandard Height of Cells = Pitch * (M-1)                Where Mrepresents the number of tracks.? is the ration between the PMOS width and NMOS width.

Standard cell library contains cells of different threshold devices (eg-Standard Vt and Hight Vt) and different drive strength (multiple fingering). Different category ofCells in universal Library1.     Basic gated (AND, OR, NOT, NAND, NOR, XOR, XNOR)2.     Half Adder and Full Adder3.     MUX4.     AOI (AND-OR-INV)5.     OAI (OR-AND-INV)6.     Clock gate7.

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     Metal Ecoable cells8.     Tie Cells 9.     Flops (D Flip flop and Scan-able flop withset/reset)10.

  Spare Cells (Fillers, Tap cells, Decaps.. etc)11.  Boolean functional cells12.  Power management cells (Isolation cell, LevelShifter, Power gate/switch) Spare CellsTap cells        Thesecells are used to provide substrate connection and avoid latch-up. The cellsused to connect n-well to VDD and p-substrate top VSS.ECO Cells               Thefiller cells which are converted to accomplish any functionality are calledmetal ECO cells. The size of these cells is more as compared to normal cells ofsame functionality.

Filler Cells               Thesecells are used to provide power rail continuity. This cells also contain psubstrate and n-well. Decoupling CapacitorCells (Decap cells)               These capused in design between power and ground rails. These cells behaves like abattery when drops present in power rail and maintain the voltage across rails.These cells aids IR drop issue and removes glitches in power.End cap cells               They areadded near the end of rows to terminate the rows properly.

Tie Cell               Thereare 2 type of TIE cell:- TIE High (give output VDD) & TIE Low (give outputVSS). In design some cell input require alogic 0 or logic 1 value. Rather than providing connection to VDD/VSS rails,you connect them to TIE cells. Tie cells are used to avoid direct connection topower rails to protect cell from damage.