Overview:- addresses for the transfer of data between outside

Overview:-8086 microprocessor is an enhanced version of 8085microprocessor that was designed by Intel in the year 1976. It is a 16-bitmicroprocessor that contains 20 address lines and 16 data lines that providesupto 1MB storage.

It consists of powerful instruction set, which providesoperations like multiplication & division.It supports two modes of operation i.e. Maximum andMinimum mode.The former one is suitable for system having multiple processors and latter is suitable for systemhaving a single processor. Feature such as Memory Segment register were firstseen in this 8086 microprocessor.It is notable as the processor used in theoriginal IBM PC deign, including the widespread version called IBM PC XT.

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 Architecture Of 8086:-Unlikemicrocontrollers, microprocessors don’t contain inbuilt memory. MostlyPrinceton architecture is used for microprocessors where data & programmemory are combined together in a single memory interface. As a microprocessordoesn’t have any inbuilt peripheral, the circuit is purely digital and theclock can be anywhere from a few MHz to a few hundred MHz or even GHz.Thisincreased clock speed  facilitatesintensive computation that a microprocessor is supposed to perform.  InternalArchitecture of 8086 microprocessor:-Intel  8086 is a 16-bit integer processor.

Itcontains 16-bit data bus & 20-bit address bus.  The lower 16-bit address lines & 16-bitdata lines are multiplexed i.e. from(AD0-AD15).Since  20-bit address lines are available,8086 canaccess upto 220 i.e. 1MB of physical memory. The internalarchitecture of Intel 8086 is divided into two units  i.

e.1.     Bus Interface Unit (BUI).2.     Execution Unit (EU).

               Basic Architecture of 8086Microprocessor is :-      Bus Interface Unit:- FunctionsOf Bus Interface Unit  is:-·       Generationof the memory.·       I/Oaddresses for the transfer of data between outside the CPU, and the EU.·       Itsends out tasks.·       It  fetches instructions  from memory.·       Itreads data from memory and ports.

·       Italso writes data from memory & ports.·       SoBIU takes  care of all the address anddata transfers on the buses.This unithandles all transfer  of data andaddresses on the buses  for theEU(Execution Unit). This unit sends out addresses, fetches  instructions from memory  ,reads data from ports and memory and writesdata to ports and memory.Different Parts Of BIU:1.

     Segment Register2.     Instruction Pointer3.     The Queue·       Segment Register :-BIU contains of four 16-bit registerregisters as follows: 1.

     Code Segment2.     Stack Segment3.     Extra Segment4.     Data Segment Function Of Segment Register :- In 8086complete 1MB memory is divided into 16 logical segments.

Each segment thuscontains 64 KB of memory. While addressing any  location in the memory  bank, first part is Segment  address ,and the second is Offset address.The  segment  registers contain 16-bit base addresses  related to different  segments.Thus the CS,DS,ES,SSsegment registers , respectively contain the segment addresses for the Code, Data, Extra and Stack segments.They may ormay not be physically separated. Each segment register contains a 16-bit baseaddress which points to the lowest- addressed byte of that particular segment in memory.

 Generation  of physical address:- Segment  address -1005HOffsetaddress-5555HSegment  address -1005H-0001 0000 0000 0101Shifted by4-bit positions-0001 0000 0000 0101 0000                                        +Offset  address – 0001 0101 0101 1010 0101   1              5       5       A          5  ·       Instruction Pointer:-1.     It is a 16-bit register , which defines location of next wordof instruction code that is to be fetched in the current code segment.2.    IP contains an offset  instead ofthe actual address of the next instruction.3.

    The 20-bit address  produced  after addition of offset stored inInstruction Pointer address  in the CS iscalled the Physical Address of the code byte.4.    IP always works together with CS register & it points to currentlyexecuting instruction. ·       The Queue:-               Last section of BIU is the FIFOgroup of  registers called a queue.It isbasically a group of registers.This arrangement makes  possible for BIU to fetch the instruction byte while EU is decoding an instruction or executing an instruction whichdoesn’t require use of buses.

This arrangement is called pipelining. This isdone to speed up the program execution.  Execution Unit:-It  receives program instruction , codes  from  BIU , executes  them and stores the results in the general registers . It can also store the datain a memory  location or send them to anI/O device by  passing the data backto  BIU. This unit, EU, has no connectionwith  system Buses. It receives and outputsall its data through BIU.

  ·       ALU (Arithmetic & Logic Unit):-The  EU unit contains a  circuit board called Arithmetic And LogicUnit. The ALU  can perform arithmetic, suchas ,”+,-,*,/” and logic such as OR,AND,NOT operations. ·       Register:-  It is like a memorylocation where exception is that these are denoted by name rather than numbers.It has 4 data registers , i.e.

, AX,BX,CX,DX and 2 pointer registers SP,BP andtwo index registers SI,DI  and onetemporary register and one status registers FLAGS. AX,BX,CX and DX registershas two 8-bit registers to access the high & low-byte data registers.High byte of AX is said to be AH & low byte is AL.Similarly, the high & low bytes of BX,CX,DX are BH & BL, CH & CL,DH respectively. All data, pointer, index and status registers are of 16bits.Else these, temporary register holds operands for ALU bits of FLAGS register reflect result of a computation.   Memory Segmentation:-The processof dividing memory into segments of various sizes is known as Memory  Segmentation. A segment is simply an area inmemory.

Since in memory, data is stored as bytes and each byte has a specificaddress. Intel 8086 microprocessor has 20 lines address bus. With 20 addresslines, memory that can be addressed is 220 bytes(220 =1,048,576bytes=1MB).

8086 canaccess memory with address that range from 00000H to FFFFF H. In 8086, memory has four different types ofsegments which are:1.     Code Segment2.     Data segment3.

     Stack Segment4.     Extra SegmentEach ofthese segments  are addressed by anaddress stored in the corresponding segment  register. These registers are 16-bit in size.Each register stores base address(starting-address) of the correspondingsegment.

Because thesegment registers can’t store 20 bits, they only store upper 16 bits. Flags  Register:-Thisregister determines the current state of the processor. They are modifiedautomatically by the CPU after mathematical operations and allows to determinetype of result, & also to determine conditions to transfer control todifferent parts of program. Generally, nobody can access these registersdirectly. 1.

     Carry Flag (CF):- This flag is set to “1” when thereis an unsigned overflow.Eg.:- On adding 255+1 ( result is notin range of 0….

255). When there is no overflow , carry flag is set to “0”.2.     Parity Flag (PF) :-  This flag is set to “1” when there is evennumber of one bits in result, and set to “0” when there is odd number of onebits in the result.3.

     Auxiliary Flag (AF):- This flag  is set to “1” when there is an unsigned flowfor low nibble i.e. 4 bits.4.     Zero Flag (ZF):- This flag is set to “1” when  result is “zero”. For non-result this flag isset to 0.5.

     Sign Flag (SF):- This flag is set to “1” when resultis negative. When result is positive, it is set to “0”.(This flag takes valueof the most significant bit). 6.     Trap Flag (TF):- This flag is used for on-chipde-bugging.

7.     Interrupt  Enable Flag (IF):- When this flag is set to “1” CPUreacts to interrupts from external devices.8.     Direction Flag (DF):-It is used  by some instructions to process data chains.

When this flag  is set to  “0”, processing is done forward or else whenthis flag is set to “1” , processing is done backward.9.     Overflow Flag :- This flag is set to “1” when thereis a signed overflow.

For example, when you add bytes 100+50 (result is not inrange – 128…127). Pin  Diagram of 8086Microprocessor:-  The 8086 can operate in two modes , theseare the minimum mode and maximum mode . For  minimum  mode , a unique  processor  system with  a single 8086 and for Maximum mode  a  multi-processor system with more than one8086.

MN/MX- is an input pin used to select one ofthis mode .when MN/MX is high the 8086 operates in minimum mode .Inthis mode the 8086 is configured to support small single processor system usinga few devices that the system bus .when MN/MX is low 8086 isconfigured to support multiprocessor system.

The AD0-AD15 lines area 16bit multiplexed addressed or data bus. During the 1st clockcycle AD0-AD15 are the low order 16Bit adders. The 8086 has a total of 20address line ,the upper 4 lines are multiplexed with the state signal that is A16/S3, A17/S4 , A18/S5 , A19 /S6.During the first clock period of a best cyclethe entire 20bit address is available on these line. During all other clockcycles for memory and i/o operations AD15-AD0 contain the 16 bit data and S3,S4,S5,S6 becomethe status line .

S3 and S4 are decoded as followsA17/S4 A16/S3 Function1.Extra Segment2.Stack Segment3.Code/No segment4. Data SegmentThere for  the 1st clock cycle of aninstruction execution the A17/S4 And A16/S3 pins specify which segment registergenerate the segment portions of the 8086 addressBHE/S7 is used as best high enable duringthe 1st click cycle of an instruction execution .the BHE can beused in conjunction with AD0 to select the memoryRD is low when the data is read from memoryor I/O location .TEST is an input pin and is only used by thewait instruction .

the 8086 enter a wait state after execution of the waitinstruction until a low is Sean on the test pin.INTR is a maskable interrupt input.NIM is the non maskable interrupt input.RESET is the system set reset input signal it terminatesall the activities it clear PSW,IP,DS,SS,ES and the instructionQueue.DT/R(Data Transmit or receive ):is an o/p signalrequired in system that uses the data bus transceiverALE is an address latch enable. Is an o/p signal provided by the 8086 and can be used todemultiplexed AD0 to AD15 in to A10 toA15 and D0 to D15.

M/IO is an 8086 output signal to distinguisha memory access and i/o access.WR is used by the 8086 for performing writememory or write i/o operation .INTA(interrupt acknowledgement signal )INTA is the interrupt acknowledgmentsignalHOLD and HOLDAa high on the HOLD pin indicates thatanother master is required to take over the S/M busCLK clock provides the basic timing signalsfor the 8086 and bus controls .                                                   FEATURES OF 8086 ·       It has an instruction queue, which is capable of storing six instruction bytes from memory resulting in faster processing. ·       It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, & also 16-bit external data bus resulting in faster processing. ·       It is available in 3 versions based on frequency of operation i.e. 1.

    8086 -> 5MHz 2.    8086 – 2->8 MHz 3.    (c) 8086-1 -> 10 MHz            It uses two stages of pipelining, i.

e. Fetch stage and Execute                        Stage, which improves performance.      F