Overview:- addresses for the transfer of data between outside


8086 microprocessor is an enhanced version of 8085
microprocessor that was designed by Intel in the year 1976. It is a 16-bit
microprocessor that contains 20 address lines and 16 data lines that provides
upto 1MB storage. It consists of powerful instruction set, which provides
operations like multiplication & division.

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It supports two modes of operation i.e. Maximum and
Minimum mode.The former one is suitable for 
system having multiple processors and latter is suitable for system
having a single processor. Feature such as Memory Segment register were first
seen in this 8086 microprocessor.It is notable as the processor used in the
original IBM PC deign, including the widespread 
version called IBM PC XT.


Architecture Of 8086:-

microcontrollers, microprocessors don’t contain inbuilt memory. Mostly
Princeton architecture is used for microprocessors where data & program
memory are combined together in a single memory interface. As a microprocessor
doesn’t have any inbuilt peripheral, the circuit is purely digital and the
clock can be anywhere from a few MHz to a few hundred MHz or even GHz.This
increased clock speed  facilitates
intensive computation that a microprocessor is supposed to perform.


Architecture of 8086 microprocessor:-

Intel  8086 is a 16-bit integer processor. It
contains 16-bit data bus & 20-bit address bus.  The lower 16-bit address lines & 16-bit
data lines are multiplexed i.e. from(AD0-AD15).

Since  20-bit address lines are available,8086 can
access upto 220 i.e. 1MB of physical memory.

The internal
architecture of Intel 8086 is divided into two units  i.e.

1.     Bus Interface Unit (BUI).

2.     Execution Unit (EU).



             Basic Architecture of 8086
Microprocessor is :-


Bus Interface Unit:-

Of Bus Interface Unit  is:-

of the memory.

addresses for the transfer of data between outside the CPU, and the EU.

sends out tasks.

It  fetches 
instructions  from memory.

reads data from memory and ports.

also writes data from memory & ports.

BIU takes  care of all the address and
data transfers on the buses.

This unit
handles all transfer  of data and
addresses on the buses  for the
EU(Execution Unit). This unit sends out addresses, fetches  instructions from memory  ,reads data from ports and memory and writes
data to ports and memory.

Different Parts Of BIU:

1.     Segment Register

2.     Instruction Pointer

3.     The Queue

Segment Register :-BIU contains of four 16-bit register
registers as follows:


1.     Code Segment

2.     Stack Segment

3.     Extra Segment

4.     Data 

 Function Of Segment Register :- In 8086
complete 1MB memory is divided into 16 logical segments. Each segment thus
contains 64 KB of memory. While addressing 
any  location in the memory  bank, 
first part is Segment  address ,
and the second is Offset address.

The  segment  registers contain 16-bit base addresses  related to different  segments.

Thus the CS,DS,ES,SS
segment registers , respectively contain 
the segment addresses for the Code, Data, Extra and Stack segments.

They may or
may not be physically separated. Each segment register contains a 16-bit base
address which points to the lowest- addressed 
byte of that particular segment in memory.


Generation  of 
physical address:-


Segment  address -1005H


Segment  address -1005H-0001 0000 0000 0101

Shifted by
4-bit positions-0001 0000 0000 0101 0000


Offset  address – 0001 0101 0101 1010 0101   

1              5       
5       A          5 


Instruction Pointer:-

 It is a 16-bit register , which defines location of next word
of instruction code that is to be fetched in the current code segment.

IP contains an offset  instead of
the actual address of the next instruction.

The 20-bit address  produced  after addition of offset stored in
Instruction Pointer address  in the CS is
called the Physical Address of the code byte.

IP always works together with CS register & it points to currently
executing instruction.


The Queue:-


              Last section of BIU is the FIFO
group of  registers called a queue.It is
basically a group of registers.This arrangement makes  possible 
for BIU to fetch the instruction byte 
while EU is decoding an instruction or executing an instruction which
doesn’t require use of buses.This arrangement is called pipelining. This is
done to speed up the program execution.


Execution Unit:-

It  receives 
program instruction , codes  &
data from  BIU , executes  them and 
stores the results in the general registers . It can also store the data
in a memory  location or send them to an
I/O device by  passing the data back
to  BIU. This unit, EU, has no connection
with  system Buses. It receives and outputs
all its data through BIU.



ALU (Arithmetic & Logic Unit):-

The  EU unit contains a  circuit board called Arithmetic And Logic
Unit. The ALU  can perform arithmetic, such
as ,”+,-,*,/” and logic such as OR,AND,NOT operations.



  It is like a memory
location where exception is that these are denoted by name rather than numbers.
It has 4 data registers , i.e., AX,BX,CX,DX and 2 pointer registers SP,BP and
two index registers SI,DI  and one
temporary register and one status registers FLAGS. AX,BX,CX and DX registers
has two 8-bit registers to access the high & low-byte data registers.

High byte of AX is said to be AH & low byte is AL.
Similarly, the high & low bytes of BX,CX,DX are BH & BL, CH & CL,DH
respectively. All data, pointer, index and status registers are of 16

Else these, temporary register holds operands for ALU &
individual bits of FLAGS register reflect result of a computation.




Memory Segmentation:-

The process
of dividing memory into segments of various sizes is known as Memory  Segmentation. A segment is simply an area in
memory. Since in memory, data is stored as bytes and each byte has a specific
address. Intel 8086 microprocessor has 20 lines address bus. With 20 address
lines, memory that can be addressed is 220 bytes(220 =1,048,576

8086 can
access memory with address that range 
from 00000H to FFFFF H.

 In 8086, memory has four different types of
segments which are:

1.     Code Segment

2.     Data segment

3.     Stack Segment

4.     Extra Segment

Each of
these segments  are addressed by an
address stored in the corresponding segment  register. These registers are 16-bit in size.
Each register stores base address(starting-address) of the corresponding

Because the
segment registers can’t store 20 bits, they only store upper 16 bits.


Flags  Register:-

register determines the current state of the processor. They are modified
automatically by the CPU after mathematical operations and allows to determine
type of result, & also to determine conditions to transfer control to
different parts of program. Generally, nobody can access these registers

1.     Carry Flag (CF):- This flag is set to “1” when there
is an unsigned overflow.

Eg.:- On adding 255+1 ( result is not
in range of 0….255). When there is no overflow , carry flag is set to “0”.

2.     Parity Flag (PF) :-  This flag is set to “1” when there is even
number of one bits in result, and set to “0” when there is odd number of one
bits in the result.

3.     Auxiliary Flag (AF):- This flag  is set to “1” when there is an unsigned flow
for low nibble i.e. 4 bits.

4.     Zero Flag (ZF):- This flag is set to “1” when  result is “zero”. For non-result this flag is
set to 0.

5.     Sign Flag (SF):- This flag is set to “1” when result
is negative. When result is positive, it is set to “0”.(This flag takes value
of the most significant bit).

6.     Trap Flag (TF):- This flag is used for on-chip

7.     Interrupt  Enable Flag (IF):- When this flag is set to “1” CPU
reacts to interrupts from external devices.

8.     Direction Flag (DF):-It is used  by some instructions to process data chains.

When this flag  is set to  “0”, processing is done forward or else when
this flag is set to “1” , processing is done backward.

9.     Overflow Flag :- This flag is set to “1” when there
is a signed overflow. For example, when you add bytes 100+50 (result is not in
range – 128…127).


Pin  Diagram of 8086



The 8086 can operate in two modes , these
are the minimum mode and maximum mode . For  minimum  mode , a unique  processor  system with  a single 8086 and for Maximum mode  a  multi-processor system with more than one

MN/MX- is an input pin used to select one of
this mode .when MN/MX is high the 8086 operates in minimum mode .In
this mode the 8086 is configured to support small single processor system using
a few devices that the system bus .when MN/MX is low 8086 is
configured to support multiprocessor system.

The AD0-AD15 lines are
a 16bit multiplexed addressed or data bus. During the 1st clock
cycle AD0-AD15 are the low order 16Bit adders. The 8086 has a total of 20
address line ,the upper 4 lines are multiplexed with the state signal that is A16/S3
, A17/S4 , A18/S5 , A19 /S6.During the first clock period of a best cycle
the entire 20bit address is available on these line. During all other clock
cycles for memory and i/o operations AD15-AD0 contain the 16 bit data and S3,S4,S5,S6 become
the status line .S3 and S4 are decoded as follows

A17/S4 A16/S3 Function

1.Extra Segment

2.Stack Segment

3.Code/No segment

4. Data Segment

There for  the 1st clock cycle of an
instruction execution the A17/S4 And A16/S3 pins specify which segment register
generate the segment portions of the 8086 address

BHE/S7 is used as best high enable during
the 1st click cycle of an instruction execution .the BHE can be
used in conjunction with AD0 to select the memory

RD is low when the data is read from memory
or I/O location .

TEST is an input pin and is only used by the
wait instruction .the 8086 enter a wait state after execution of the wait
instruction until a low is Sean on the test pin.

INTR is a maskable interrupt input.

NIM is the non maskable interrupt input.

RESET is the system set reset input signal it terminates
all the activities it clear PSW,IP,DS,SS,ES and the instruction

DT/R(Data Transmit or receive ):is an o/p signal
required in system that uses the data bus transceiver

ALE is an address latch enable
. Is an o/p signal provided by the 8086 and can be used to
demultiplexed AD0 to AD15 in to A10 toA15 and D0 to D15.

M/IO is an 8086 output signal to distinguish
a memory access and i/o access.

WR is used by the 8086 for performing write
memory or write i/o operation .

INTA(interrupt acknowledgement signal )

INTA is the interrupt acknowledgment


a high on the HOLD pin indicates that
another master is required to take over the S/M bus

CLK clock provides the basic timing signals
for the 8086 and bus controls .

·       It has an instruction queue, which is capable of storing
six instruction bytes from memory resulting in faster processing.
·       It was the first 16-bit processor having 16-bit ALU,
16-bit registers, internal data bus, & also 16-bit external data bus
resulting in faster processing.
·       It is available in 3 versions based on frequency of
operation i.e.
8086 -> 5MHz
8086 – 2->8 MHz
(c) 8086-1 -> 10 MHz
           It uses two stages of
pipelining, i.e. Fetch stage and Execute                        Stage, which
improves performance.