Inthe last two decades IC designs for signal processing applications have beenrapidly growing.
So, the requirement for a low power ,small area,mediumresolution (10-12 bits) analog-to-digital converters with low-to-medium speedsis expanding. Flash and pipelined ADCarchitectures are used for high speed conversion systems whereas SAR and sigmadelta ADCs arec used for low-to-medium speed systems. The flash ADC uses 2n-1 comparators for an nbit resolution, which means the number of comparators doubles with the additionof each 1-bit resolution. This usage of much number of comparators increase thearea occupied and the power consumed by the ADC. Hence the Flash ADC is limited8 bits.The pipelined ADC architecture isused for video processing & wireless receivers applications.
They can beused upto a resolution of 8-12 bits and sampling speed of 200 MS/s.. Thelimitations of the architecture are high power consumption and the large switchcapacitor network requied at high resolutions. TheSAR ADCs on the other hand can be designed up to 10-14 bits.
The operation ofthis ADC mainly depends on the digital to analog converter and the binarysearch algorithm it uses. The limitations are the low speed of the SAR ADC dueto its sequential operation and the capacitor mismatches of the switched capacitorcircuit used in the DAC at high resolutions.To overcome the limitations researchhas been done on various hybrid ADC models to improve the accuracy, power, and speed. The introduced pipelined-SAR ADCarchitecture improves both power and conversion efficiency but the speed ofthis ADC is less compared to the SAR ADC due to the additional interstage gainamplifier. The other limitations of this architecture are high powerconsumption due to the DAC within the stage and capacitor mismatches. The flah-SAR ADC architecture gives an improved conversion rate without addingadditional complexity and power consumption.
But, this architecture is alsolimited at higher resolutions because of the higher number of comparatorsrequired for the flash and the higher order DAC required for the SAR ADC.This paper presents Two-Step SAR-flash ADC architecture for improvedconversion accuracy with lower power consumption and smaller area. It canachieve a speed upto 200 MS/s without affecting the accuracy. This is a 12-bitADC which contains two identical 6-bit SAR-Flash ADCs connected by a interstagegain amplifier. The 6-bit SAR-Flash ADC contains a of 3-bit SAR ADC followed by a 3-bit flashADC. This improves the performance due to the reduced capacitor mismatcheffects and the less number of comparators used in the flash.
The detailedarchitecture with time operation of this ADC design is described in the nextsections.